1. Field of the Invention
The present invention relates to a plasma display device and a capacitive load capacitive load driving circuit.
2. Description of the Related Art
The plasma display apparatus has been put to practical use as a flat display and is a thin display with high luminance. FIG. 1 is a diagram showing the general constitution of a three-electrode AC-driven plasma display apparatus. As shown schematically, the plasma display apparatus comprises a plasma display panel (PDP) 1 consisting of two substrates between which a discharge gas is enclosed, each substrate having a plurality of X electrodes (X1, X2, X3, . . . , Xn) and a plurality of Y electrodes (Y1, Y2, Y3, . . . , Yn) arranged adjacently by turns, a plurality of address electrodes (A1, A2, A3, . . . , Am) arranged in the direction perpendicular to the X and Y electrodes and phosphors arranged at the crossings, an address driver 2 which applies an address pulse or the like to the address electrode, an X common driver 3 which applies a sustain discharge pulse or the like to the X electrodes, a scan driver 4 which applies a scan pulse or the like sequentially to the Y electrodes, a Y common driver 5 which supplies a sustain discharge pulse or the like, to be applied to the Y electrodes, to the scan driver 4, and a control circuit 6 which controls each part, wherein the control circuit 6 has a display data control section 7 which further includes a frame memory and a drive control circuit 8 including a scan driver control section 9 and a common driver control section 10. The display data control section 7 inputs a clock CLK and a display data DATA, and the drive control circuit 8 inputs a vertical sync signal Vsync and a horizontal sync signal Hsync. The X common driver 3 and the Y common driver 5 respectively include sustain circuits which output sustain pulses, and each sustain circuit has a sustain output element. As the plasma display apparatus is widely known, a detailed description about the whole apparatus is not given here but only the X common driver 3 and the Y common driver 5 relating to embodiments of the present invention are described here.
FIG. 2 is a block diagram showing the general constitution of the power transistor drive circuit disclosed in the Patent document 1 stated below, and the whole is provided in an IC 11 as shown by the dotted line. In the plasma display apparatus, the power transistor drive IC in FIG. 2 is used as a pre-drive circuit for driving a sustain output element. In the power transistor drive IC 11 shown in FIG. 2, a high level input voltage HIN is amplified in an input amplifier circuit 21, converted into a voltage referred to a high level reference voltage Vr in a high level shift circuit 22, and outputted as a high level output voltage HO via an output amplifier circuit 23. On the other hand, a low level input voltage LIN is amplified in an input amplifier circuit 24 and outputted as a low level output voltage LO after input into an output amplifier circuit 26 via a delay circuit 25 and amplified therein. Reference numbers 12 and 13 respectively denote input terminals of the high level input voltage HIN and the low level input voltage LIN, reference number 16 and 19 respectively denote output terminals of the high level output voltage HO and the low level output voltage LO, reference number 15 denotes a supply terminal of a high level supply voltage Vc, reference number 17 denotes a supply terminal of the high level reference voltage Vr, reference number 18 denotes a supply terminal of a low level supply voltage vd, and reference number 20 denotes a ground terminal.
In the power transistor drive IC shown in FIG. 2, the delay circuit 25 serves to adjust the difference tdLH (HO) in the rise times between the high level input voltage HIN and the high level output voltage HO and the difference tdLH (LO) in the rise times between the low level input voltage LIN and the low level output voltage LO so that they are equal. Moreover, the delay circuit 25 also serves to adjust the difference tdHL (HO) in the fall times between the high level input voltage HIN and the high level output voltage HO and the difference tdHL (LO) in the fall times between the low level input voltage LIN and the low level output voltage LO so that they are equal. However, it is impossible for the delay circuit 25 to make tdLH (HO) and tdLH(LO) coincide with each other perfectly, and it is inevitable that a certain difference occurs. Similarly, it is also impossible to make tdHL(HO) and tdHL(LO) coincide with each other perfectly, and it is inevitable that a certain difference occurs.
When the power transistor drive IC shown in FIG. 2 is used as a pre-drive circuit in a plasma display apparatus, sustain output elements such as a power MOSFET and an IGBT (Insulated Gate Bipolar Transistor) are connected to the output terminals 16 and 19. In a plasma display apparatus (PDP apparatus), a sustain pulse is generated, by turning on/off a sustain output element, and is supplied to the X electrode and the Y electrode of a plasma display panel (PDP).
FIG. 3 shows an example of a sustain circuit in a PDP apparatus, where the power transistor drive IC in FIG. 2 is used as a pre-drive circuit 11A and a pre-drive circuit 11B of the sustain output elements. In FIG. 3, CU and CD denote the sustain output elements, and by turning on/off these output elements, a sustain pulse is supplied to the PDP corresponding to a capacitive load. In FIG. 3, an input signal CUI is inputted as a high level input voltage of the pre-drive circuit 11A and supplied to the output element CU as a high level output voltage. On the other hand, an input signal CDI is inputted as a low level input voltage of the pre-drive circuit 11A and supplied to the output element CD as a low level output voltage.
When the output element CU is turned on, a supply voltage Vs is supplied to the PDP via a diode D1 and the output element CU (at this time the output element CD is off). When the output element CD is turned on, a ground (GND) voltage is supplied to the PDP via the output element CD (at this time the output element CU is off). On the other hand, the supply voltage of the pre-drive circuit 11A for driving the output element CU (high level supply voltage maintained across a capacitor C1) is charged across the capacitor C1 from a power supply Ve via a diode D2. The supply voltage of the pre-drive circuit 11A for driving the output element CD (low level supply voltage maintained across a capacitor C2) is charged directly across the capacitor C2 from the power supply Ve. In the circuit shown in FIG. 3, a sustain pulse is supplied to the PDP by turning on/off the output elements CU and CD alternately.
LU and LD in FIG. 3 are power recovery output elements and the power supplied to the PDP through the CU and CD is reduced by turning on/off the LU and the LD. In FIG. 3, an input signal LUI is inputted as a high level input voltage of the pre-drive circuit and supplied to the output element LU as a high level output voltage. An input signal LDI is inputted as a low level input voltage of the pre-drive circuit and supplied to the output element LD as a low level output voltage.
When the output element LU is turned on, a middle point voltage Vp of capacitors C5 and C6 connected in series between the supply voltage Vs and the GND is supplied to the PDP via the output element LU, a diode D4 and a coil L1 (at this time, the output element LD is off). On the other hand, when the output element LD is turned on, the above-mentioned middle point voltage Vp is supplied to the PDP via a coil 2, a diode D5 and the output element LD (at this time, the output element LU is off). The supply voltage (high level supply voltage maintained across a capacitor C3) of the pre-drive circuit for driving the output element LU is charged across the capacitor C3 from the power supply Ve via a diode D3. On the other hand, the supply voltage (low level supply voltage maintained across a capacitor C4) of the pre-drive circuit for driving the output element LD is charged across the capacitor C4 directly from the power supply Ve. In the circuit shown in FIG. 3, the output element LU is turned on immediately before the sustain output element CU is turned on, and the output element LD is turned on immediately before the output element CD is turned on and, thus, the power loss caused by the CU and the CD is reduced.
In the circuit shown in FIG. 3, a switch SW1 is turned on during the reset period of the plasma display apparatus and serves to supply a reset voltage Vw to the PDP via the output element CU.
Furthermore, in the patent document 2 below, a description is given on a method and a circuit for driving power transistors and integrated circuits including the above circuit.
[Patent document 1] Japanese Patent Application Laid-Open No. 2004-274719
[Patent document 2] Japanese Patent No. 3069043
In the circuit shown in FIG. 2 great variations in delay time may be caused by slow transmission speed. As a result there has been a need to keep long a period like a gap in time (a period in which both CU and CD are kept being turned off) in order to ensure the timing margin between the driving pulse to be supplied to the high side element CU of the sustain output elements and the driving pulse to be supplied to the low side element CD of the sustain output elements. This has been the obstacle to reducing of a sustain period to increase the number of the sustaining pulse.
Furthermore, great delay time to be caused, as the case may be, would lead to a larger variation in on-timing between the element for the electric power recovery LU and the high side element CU of the sustain output elements and a variation in on-timing between the element for the electric power recovery LD and the low side element CD of the sustain output elements, with the result that there has been the probability of decrease in the electric power recovery efficiency. Furthermore, reduction in the driving margin in the ALIS method poses a problem.
In order to overcome this problem, there has been a need to carry out a phase adjustment or the like, resulting in an increase in cost due to the phase adjustment circuit to be provided additionally and increase in the adjustment man-hour.